One problem addressed by this disclosure is to provide detection circuitry that (i) senses high-voltage power-supply-referenced signals over a wide range of power-supply voltages, specifically voltages above the detection circuit's VDD-based voltage domain including voltages above which known circuit techniques are effective and (ii) also has hot-plug (hot-swap) compatibility. Operation over a wide range of power-supply voltages means that proper operation at many different supply voltages is supported. For example, in certain embodiments, the detection circuit should operate for a supply voltage of 12V (+/−10%) and any other system supply voltage down to 5V (+/−10%) or less. In order to monitor voltages during power supply ramp up, the detection circuit should operate at the lowest voltage achievable. Other techniques that are not part of this disclosure can be used for voltages below which the embodiments of this disclosure are operable.
Techniques for establishing accurate reference voltages, regardless of the exact application, are well known to those skilled in the art of integrated circuit design. The accuracy of the reference voltage should be maintained over all operating conditions, including the VDD supply voltage of the detection circuit.
FIG. 1 shows a schematic block diagram of a prior-art over-current detection circuit 100 which senses current flow (I2) from a supply voltage VIN through a power PFET (p-type field-effect transistor) switch 150 to drive load circuitry (not shown) at the load side of the switch at voltage VOUT. Supply voltage VIN and the load circuitry at node VOUT are often at voltages significantly higher than the supply voltage VDD for the detection circuit. Resistor Rtrip (internal to the detection circuit) and resistor Rsense (external to the detection circuit) are both connected to input voltage VIN, such that the sensed voltage Vsense at the output of resistor Rsense can be compared to the trip-point (reference) voltage Vtrip at the output of resistor Rtrip to sense which voltage amplitude is greater as referenced to input voltage VIN. For relatively low, positive voltages at node VIN, the trip-point voltage Vtrip is less than the sensed voltage Vsense, and the output 137 of comparator 136 is low. For relatively high, positive VIN voltages, the trip-point voltage Vtrip is greater than the sensed voltage Vsense, and the comparator output 137 is high to indicate an over-current condition sensed at the two comparator inputs. In the implementation of FIG. 1, when an over-current condition is sensed, comparator 136 sets a latch 140, which turns off the power PFET 150 to protect the load circuitry at node VOUT.
As shown in FIG. 1, the comparator trip-point voltage Vtrip is generated by a reference-voltage generation circuit 110. In particular, amplifier 112 forces the voltage across resistor R0, sensed at the amplifier's negative input, to be equal to fixed reference voltage Vref from bandgap circuit 111, causing current I1 to flow through resistor R0, NFET (n-type FET) device NFET1, and resistor Rtrip, such that Vref=I1*R0. The resultant voltage across resistor Rtrip is Vref*(Rtrip/R0). Note that reference-voltage generation circuit 110 is referenced to the input voltage VIN, while bandgap circuit 111 is referenced to the detection circuit's ground VSS.
Reference-voltage generation circuit 110 causes the trip-voltage Vtrip to track changes in the input voltage VIN such that the voltage drop across resistor Rtrip is constant, independent of VIN, as long as device NFET1 operates within an allowable voltage range set by device parameters and the integrated circuit technology limits. As the drain-to-source voltage of device NFET1 approaches technology limits, generation of hot-electron currents from drain to substrate begins to occur. The hot-electron current is an additional current flow through resistor Rtrip, resulting in an undesired increase in the voltage drop across resistor Rtrip resulting in a measurement error at comparator 136. This limits the range of input voltage VIN over which detection circuit 100 performs within specification. As input voltage VIN increases, hot-electron currents eventually increase to the point of device failure.
FIG. 2 shows a schematic diagram of a prior-art programmable reference-voltage generation circuit 210 that can be used in detection circuit 100 of FIG. 1 in place of reference-voltage generation circuit 110. Reference-voltage generation circuit 210 extends the allowable VIN voltage range of detection circuit 100 and also provides reference-voltage programmability. Note that, in reference-voltage generation circuit 210, bandgap circuit 211, amplifier 212, device NFET1, and resistors R0 and Rtrip are analogous to the corresponding, similarly labeled elements of reference-voltage generation circuit 110 of FIG. 1.
Reference-voltage generation circuit 210 provides programmability of the voltage across resistor Rtrip. In the implementation of FIG. 2, programmable current capability is provided by the combination of programmable cascode PFET current mirror 213 and programmable cascode NFET current mirror 214.
Programmable cascode PFET current mirror 213 has a master leg (formed from PFET mirror device PM1 and PFET cascode device PC1), a permanent slave leg (formed from PFET mirror device PM3, PFET cascode device PC3, and PFET switch device PS3), and a programmable slave leg (formed from PFET mirror device PM2, PFET cascode device PC2, and PFET switch device PS2). Since the gate of switch device PS3 is tied to ground node VSS, switch device PS3 is always on, and the permanent slave leg always draws current (that is, whenever supply node VDD is powered). On the other hand, the gate of switch device PS2 is tied to control signal enb2xp. For the particular (exemplary) implementation of FIG. 2 in which all of the mirror legs have the same current strength, when control signal enb2xp is high, switch device PS2 is off, the programmable slave leg does not draw current, and PFET current mirror 213 generates an output current equal to I1. When control signal enb2xp is low, switch device PS2 is on, the programmable slave leg does draw current, and PFET current mirror 213 generates an output current equal to 2*I1.
Similarly, programmable cascode NFET current mirror 214 has a master leg (formed from NFET mirror device NM1 and NFET cascode device NC1), a permanent slave leg (formed from NFET mirror device NM2, NFET cascode device NC2, and NFET switch device NS2), and three (i.e., first, second, and third) programmable slave legs (each formed from NFET mirror device NMi, NFET cascode device NC1, and NFET switch device NSi, where i=3,4,5). Note that any currents through the four slave legs of NFET current mirror 214 are summed at node Vtrip such that the resulting, cumulative current flows through resistor Rtrip. Since the gate of switch device NS2 is tied to supply node VDD, switch device NS2 is always on and the permanent slave leg always draws current (that is, whenever supply node VDD is powered). On the other hand, the gates of switch devices NS3, NS4, and NS5 are respectively tied to control signals en0, en1, and en2. For the particular implementation of FIG. 2 in which all of the mirror legs have the same current strength, except for the third slave leg whose current strength is double, control signals en0, en1, and en2 can be programmed to selectively turn on and off different programmable slave legs to achieve, in combination with the programmability of PFET current mirror 213, any current through resistor Rtrip from I1 to 10*I1 in increments of I1, such that the minimum voltage across Rtrip is Vref*(Rtrip/R0), and the maximum voltage is 10*Vref*(Rtrip/R0).
Note that, in the architecture of reference-voltage generation circuit 110 of FIG. 1, the current flowing through resistor R0 and device NFET1 also flows through resistor Rtrip. In the architecture of reference-voltage generation circuit 210 of FIG. 2, however, the current flowing through resistor R0 and device NFET1 is mirrored by PFET current mirror 213, and the resulting mirrored current is itself mirrored by NFET current mirror 214, which generates the current that flows through resistor Rtrip.
Configured between the four slave legs of NFET current mirror 214 and resistor Rtrip is a set 215 of four corresponding high-voltage NFET cascode devices NB2-NB5 whose gates are driven by a high-voltage cascode bias signal 216 generated by a PFET divide-by-2 voltage divider 217 formed by two matched, long-gate PFET devices PD1 and PD2. As such, the voltage applied to the gates of cascode devices NB2-NB5 is always one half of the input voltage VIN. As a result, for positive-threshold transistors, the source voltages of cascode devices NB2-NB5 will always be less than one half of voltage VIN, thus limiting the drain voltages of the NFET switch devices NS2-NS5, as well as the drain voltages of the rest of the devices in NFET current mirror 214, also to be less than one half of voltage VIN.
The maximum drain-source voltage across the high-voltage cascode devices NB2-NB5, added to the allowable voltage across the programmable NFET mirror structure, increases the maximum input voltage VIN for which the reference voltage Vtrip generated by reference-voltage generation circuit 210 is stable. As such, using reference-voltage generation circuit 210 instead of reference-voltage generation circuit 110 in detection circuit 100 of FIG. 1 extends the operating range of the detection circuit to higher levels of input voltage VIN. Nevertheless, it is desirable to extend that detection circuit operating range even beyond that which can be achieved using reference-voltage generation circuit 210.